Lee, Youngjoo

Lee, YoungjooProfessor

Education
  • 2010~2014KAIST (졸업-전기 및 전자공학 )
  • 2008~2010KAIST (졸업-전기 및 전자공학 )
  • 2003~2008KAIST (졸업-전기 및 전자공학 )
Career
  • 2015~2016Assistant Professor (광운대학교 전자공학 )
  • 2014~2015Researcher, IMEC, Leuven, Belgium
Profession
  • Microprocessor architectures
  • Embedded SoC designs and optimizations
  • Ultra-low-power design methodologies
  • Advanced algorithms for embedded solutions
Journal Papers
  • 2017

    • [Accepted] Youngjoo Lee, Taehyoun Oh, and In-Cheol Park, “Mismatch-tolerant capacitor array structure for junction-splitting SAR analog-to-digital conversion,” IEIE Journal of Semiconductor Technology and Science.
    • [Accepted] Meng Li, Liesbet Van der Perre, Wim Van Thillo, and Youngjoo Lee, “Energy-efficient reconfigurable FEC processor for multi-standard wireless communication systems,” IEIE Journal of Semiconductor Technology and Science.
    • [Accepted] Esther Kim, Youngjoo Lee, and Taehyoun Oh, “A 2-8 GHz adaptive duty-cycle corrector loop with background calibration,” International Journal of Electronics.
    • Byeonggil Park, Seungyong An, Jongsun Park, and Youngjoo Lee, “Novel folded-KES architecture for high-speed and area-efficient BCH decoders,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 5, pp. 535-539.
    • Mingu Park, Kyoungho Yoo, Yunho Park, and Youngjoo Lee, “Diagonally-reinforced lane detection scheme for high-performance advanced driver assistance systems,” IEIE Journal of Semiconductor Technology and Science, vol. 17, no. 1, pp. 79-85, Feb. 2017.

    2016

    • Seokha Hwang and Youngjoo Lee, “Sharpness-aware evaluation methodology for haze-removal processing in automotive systems,” IEIE Transactions on Smart Processing and Computing, vol. 5, no. 6, pp. 390-394, Dec. 2016.
    • Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, “Low-power parallel Chien search architecture using a two-step approach,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 3, pp. 269-273, Mar. 2016.
    • Youngjoo Lee, Jaehwan Jung, and In-Cheol Park, “Energy-scalable 4KB LDPC decoding architecture for NAND-flash-based storage systems,” IEICE Transactions on Electronics, vol. E99-C, no. 2, pp. 293-301, Feb. 2016.
    • Youngjoo Lee, Meng Li, and Liesbet Van der Perre, “Memory-reduced turbo decoding architecture using NII metric compression,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 211-215, Feb. 2016.

    2015

    • Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, “Efficient parallel architecture for linear feedback shift registers,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 11, pp. 1068-1072, Nov. 2015.
    • Hyeji Kim, Youngjoo Lee, and Ji-Hoon Kim, “Low-complexity CRC-aided early stopping unit for parallel turbo decoder,” Electronics Letters, vol. 51, no. 21, pp. 1660-1662, Oct. 2015.
    • Meng Li, Youngjoo Lee, Yanxiang Huang, and Liesbet Van der Perre, “Area and energy efficient 802.11ad LDPC decoding processor,” Electronics Letters, vol. 51, no. 4, pp. 339-341, Feb. 2015.
    • Youngjoo Lee, Bongjin Kim, Jaehwan Jung, and In-Cheol Park, “Low-complexity tree architecture for finding the first two minima,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 1, pp. 61-64, Jan. 2015.

    2014

    • Jaehwan Jung, Youngjoo Lee, and In-Cheol Park, “Area-efficient method to approximate two minima for LDPC decoders,” Electronics Letters, vol. 50, no. 23, pp. 1701-1702, Nov. 2014.
    • Youngjoo Lee and In-Cheol Park, “Single-step glitch-free NAND-based digitally controlled delay lines using dual loops,” Electronics Letters, vol. 50, no. 13, pp. 930-932, June 2014.
    • Youngjoo Lee, Hoyoung Yoo, Injae Yoo, and In-Cheol Park, “High-throughput and low-complexity BCH decoding architecture for solid-state drives,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1183-1187, May 2014.

    2013

    • Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, “A 2.74-pJ/bit, 17.7-Gb/s iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash memory,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2531-2540, Oct. 2013.

    2011

    • Youngjoo Lee, Hoyoung Yoo, and In-Cheol Park, “Low-complexity parallel Chien search structure using two-dimensional optimization,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 8, pp. 522-526, Aug. 2011.
    • Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, “Area-efficient syndrome calculation for strong BCH decoding,” Electronics Letters, vol. 47, no. 2, pp. 107-108, Jan. 2011.

    2010

    • Tae-Hwan Kim, Young-Joo Lee, and In-Cheol Park, “Design of a scalable and programmable sound synthesizer,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 6, pp. 875-886, June 2010.