▣ Title : Design Techniques for Dense Embedded Memory in Advanced CMOS Technologies

▣ Abstract : On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate static power penalty. Demand for denser memories only going to increase as the number of cores in a microprocessor goes up with technology scaling. 6T SRAMs have been the embedded memory of choice for modern microprocessors due to their logic compatibility, high speed, and refresh-free operation. However, the relatively large cell size and ratioed operation make aggressive scaling of 6T SRAMs challenging in sub-22 nm. Recently, 1T1C embedded DRAMs (eDRAMs) have replaced SRAMs in several server applications reducing the footprint and improving performance. Difficulties in scaling the storage capacitor and the additional process steps involved in manufacturing the thick oxide (TOX) access devices are currently limiting the wide spread adoption of 1T1C technology.

In this talk, circuit techniques and simulation methodologies are presented to demonstrate the potential of alternative options of gain cell (2T/3T) eDRAMs and spin-torque-transfer magnetic RAMs (STT-MRAMs) for high density embedded memories. Three unique test chips of gain cell eDRAMs achieve overall faster system performances and lower static power dissipations than SRAMs in a generic 65 nm low-power (LP) CMOS process. Studies based on the proposed STT-MRAM simulation methodology show that in-plane STT-MRAMs will outperform SRAMs from 15 nm node, while its perpendicular counterpart requires further innovations in MTJ material properties in order to overcome the poor write performance from 22 nm node.