Kyungjun Min, Seonghyun Park (Integrated Program), and Hyunwoo Park (Master’s Program), students under the supervision of Professor Seokhyeong Kang at POSTECH’s Department of Electrical Engineering, received the “2024 ISOCC Best Poster Award” at the 21st International SoC Conference (ISOCC 2024) held in Sapporo, Japan, from August 19 to August 22, 2024.

Their research, titled VeriLogos, utilizes a large language model (LLM) to generate Verilog RTL code that is both grammatically and functionally accurate, as well as optimized for Post-Synthesis PPA (Power, Performance, Area) metrics. VeriLogos helps reduce errors when humans write code, accelerates the design process, and lowers the entry barriers for Verilog HDL coding, making it a valuable contribution. The excellence of this research earned them the award.