Baek, Rock-Hyun

Baek, Rock-HyunProfessor

Education
  • 2006~2011포항공과대학교 (졸업-전자전기공학)
  • 2004~2006포항공과대학교 (졸업-전자전기공학)
  • 2001~2004고려대학교 (졸업-전자전기공학)
Career
  • 2015~2016삼성전자 (Senior Device Engineer)
  • 2013~2015Circuit characterization Engineer (SEMATECH)
  • 2011~2013Post Doctoral Researcher (SEMATECH)
  • 2012~2014Project Manager of QUALCOMM associate member project
Profession
  • Technology Node Benchmarking & Tech Definition: Technology Enablement
  • Device Physics and Modeling: Scaling Issues
  • Device Characterization: H/W measurement & analysis
  • Device Fabrication: Silicon (collaborating with Prof. Jeong-Soo Lee, NDPL lab, POSTECH EE & NINT http://www.nano.or.kr)
more
Journal Papers

  • International Journals (*corresponding)

    1. J.-S.Yoon, C.-K. Baek, and R.-H. Baek*, “Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics,” IEEE Trans. Electron Devices, vol. 63, no. 9, pp. 3399-3405, Sept. 2016.

    2. R.-H. Baek, J. S. Kim, D.-K. Kim, T.-W. Kim, and D.-H. Kim, “High-Performance Logic Transistor DC Benchmarking Toward 7 nm Technology-Node Between III-V and Si Tri-gate n-MOSFETs Using Virtual-Source Injection Velocity Model,” Solid-State Electronics, vol. 116, pp. 100-103, Feb. 2016.

    3. J.-S. Yoon, E.-Y. Jeong, C.-K. Baek, Y.-R. Kim, J.-H. Hong, J.-S. Lee, R.-H. Baek*, and Y.-H. Jeong, “Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node,” IEEE Electron Device Lett., vol. 36, no. 10, pp.994-996, Oct. 2015.

    4. E.-Y. Jeong, J.-S. Yoon, C.-K. Baek, Y.-R. Kim, J.-H. Hong, J.-S. Lee, R.-H. Baek*, and Y.-H. Jeong, “Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3441-3444, Oct. 2015.

    5. J. H. Hong, S. H. Lee, Y. R. Kim, E. Y. Jeong, J. S. Yoon, J. S. Lee, R.-H. Baek*, and Y.-H. Jeong, “Impact of Spacer Dielectric Constant on Parasitic RC and Design Guidelines to Optimize DC/AC Performance in 10 nm Node Si-Nanowire FETs,” Japanese Journal of Applied Physics, vol. 54, pp. 04DN08-1~5, Feb. 2015.

    6. E.-Y. Jeong, M. J. Deen, C.-H. Chen, R.-H. Baek*, J.-S. Lee and Y.-H. Jeong, “Physical DC and Thermal Noise Models of 18 nm Double-Gate Junctionless pMOSFETs for Low Noise RF Applications,” Japanese Journal of Applied Physics, vol. 54, pp. 04DC08-1~6, Feb. 2015.

    7. R.-H. Baek, C. Y. Kang, C.-W. Sohn, Dae M. Kim, and P. Kirsch, “Investigation of Process-Induced Performance Variability and Optimization of the 10 nm Technology Node Si Bulk FinFETs,” Solid-State Electronics, vol. 96, pp. 27-33, June, 2014.

    8. K. Majumdar, S. Vivekanand, C. Huffman, K. Matthews, T. Ngai, C. H. Chen, R.-H. Baek, W. Y. Loh, M. Rodgers, H. Stamper, S. Gausepohl, C. Y. Kang, C. Hobbs, and P. D. Kirsch, “STLM: A Sidewll TLM Strucutre for Accurate Extraction of Ultralow Specific Contact Resistivity,” IEEE Electron Device Lett., vol. 34, no. 9, pp.1082-1084, Sep. 2013.

    9. C.-W. Sohn, C. Y. Kang, R.-H. Baek, D.-Y, Choi, H. C. Sagong, E.-Y. Jeong, C.-K. Baek, J.-S. Lee, Lee. J. C, and Y.-H. Jeong, “Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications,” IEEE Electron Device Lett., vol. 33, no. 9, pp.1234-1236, Sep. 2012.

    10. C. H. Park, M. D. Ko, K. H. Kim, R.-H. Baek, C. W. Sohn, C. K. Baek, S. Park, M. J. Deen, Y. H. Jeong, and J. S. Lee, “Electrical characteristics of 20-nm junctionless Si nanowire transistors,” Solid-State Electronics, vol. 73, pp. 7-10, Jul. 2012.

    11. R.-H. Baek, C. K. Baek, H.-S. Choi, J.-S. Lee, Y. Y. Yeoh, K. H. Yeo, D.-W. Kim, Kinam Kim, Dae M. Kim, and Y. H. Jeong, “Characterization and modeling of 1/f noise in Si-nanowire FETs: effect of cylindrical geometry and different processing of oxides,” IEEE Trans. Nanotechnol., vol. 10, no. 3, pp. 417-423, May. 2011.

    12. R.-H. Baek, C.-K. Baek, S.-H. Lee, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, D.-W Kim, J.-S. Lee, Dae M. Kim, and Y. H. Jeong, “C-V Characteristics in Undoped Gate-All-Around Nanowire FET Array,” IEEE Electron Dev., Lett., vol. 32, no. 2, pp. 116-118, Feb. 2011.

    13. R.-H. Baek, C. K. Baek, S.-W. Jung, Y. Y. Yeoh, D.-W. Kim, J.-S. Lee, Dae M. Kim, and Y. H. Jeong, “Characteristics of the Series Resistance Extracted from Si Nanowire FETs Using the Y-Function Technique,” IEEE Trans. Nanotechnol., vol. 9, no. 2, pp. 212-217, Mar, 2010.

    14. R.-H. Baek, C. K. Baek, S. W. Jung, Y. Y. Yeoh, D. W. Kim, J. S. Lee, D. M. Kim, and Y. H. Jeong, “Comparison of Series Resistance and Mobility Degradation Extracted from n- and p-Type Si-Nanowire Field Effect Transistors Using the Y-Function Technique,” Japanese Journal of Applied Physics, vol. 49, pp. 04DN06-1~5, Apr. 2010.

    15. S. H. Song, H.-S. Choi, R.-H. Baek, G.-B. Choi, M.-S. Park, K. T. Lee, H. C. Sagong, S.-H. Lee, S. W. Jung, C. Y. Kang, and Y.-H. Jeong, “A new physical 1/f noise model for double stack high-k gate dielectric MOSFETs,” IEEE Electron Device Lett., vol. 30, No. 12, pp. 1365-1367, Dec. 2009.

    16. H. S. Choi, S. H. Hong,R.-H. Baek, K. T. Lee, C. Y. Kang, R. Jammy, B. H. Lee, S. W. Jung, and Y. H. Jeong, “Low-Frequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate Dielectric,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 523-525, May 2009.

    17. K. T. Lee, C.Y. Kang, H-S. Choi, S-H. Hong, G-B. Choi, J.C. Kim, S-H. Song, R.-H. Baek, M-S. Park, H.C. Sagong, B.H. Lee, G. Bersuker, H-H. Tseng, R. Jammy, Y-H. Jeong, “A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 Gate Stack nMOSFETs”, Microelecton. Eng., 88, pp. 3411-3414, Aug. 2009.

    18. S. H. Hong, G. B. Choi, R.-H. Baek, H. S. Kang, S. W. Jung, and Y. H. Jeong, “Low-temperature performance of nanoscale MOSFET for deep-space RF applications,” IEEE Electron Device Lett., vol. 29, no. 7, pp. 775-777, Jul 2008.

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