국제전문학술지

• An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 62, 1335-1344 (2015)
• A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer, IEEE Transactions on Biomedical Circuits and Systems, , 9, 138-151 (2015)
• EMI Issues in Pseudo-Differential Signaling for SDRAM Interface, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 455-462 (2015)
• An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 404-416 (2015)
• An In-Band Noise Filtering 32-tap FIR-Embedded Delta Sigma Digital Fractional-N PLL, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 342-348 (2015)
• An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 326-333 (2015)
• Cost-Efficient and Automatic Large Volume Data Acquisition Method for On-Chip Random Process Variation Measurement, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 184-193 (2015)
• An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 15, 155-167 (2015)
• Analytical Formulas for Tradeoff Among Channel Loss, Length, and Frequency of RC- and LC-Dominant Single-Ended Interconnects for Fast Equalized Link Tradeoff Estimation, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, , 5, 1497-1506 (2015)
• An LCD-VCOM-Noise Resilient Mutual-Capacitive Touch-Sensor IC Chip With a Low-Voltage Driving Signal, IEEE SENSORS JOURNAL, , 15, 4595-4602 (2015)
• The Oscillation Frequency of CML-based Multipath Ring Oscillators, Journal of Semiconductor Technology and Science, , 15, 671-677 (2015)
• A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 14, 579-587 (2014)
• A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 987-991 (2014)
• A 0.5-V, 1.47-mu W 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 840-844 (2014)
• An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49, 2618-2630 (2014)
• An Approximate Closed-Form Channel Model for Diverse Interconnect Applications, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, , 61, 3034-3043 (2014)
• Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 61, 481-485 (2014)
• Current-Mode Transceiver for Silicon Interposer Channel, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 49, 2044-2053 (2014)
• Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY Interface, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 14, 463-470 (2014)
• An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, , 8, 799-809 (2014)
• A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier, IEEE Trans. on Circuits and Systems-II, , 60, 142-146 (2013)
• A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, , 60, 91-95 (2013)
• A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation, IEEE Journal of Solid-State Circuits, , 48, 2118-2127 (2013)
• A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL, IEEE Journal of Solid-State Circuits, , 48, 2795-2804 (2013)
• A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design, Journal of Semiconductor Technology and SCience, , 13, 482-491 (2013)
• A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise Cancellation, IEEE Transaction on circuits and Systems II, , 59, 721-725 (2012)
• An Energy-efficient Equalized Transceiver for RC-dominant Channels, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 45, 1186-1197 (2010)
• A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS, , 44, 3526-3538 (2009)
• Characterization of Equalized and Repeated Interconnects for NoC Applications, IEEE DESIGN & TEST OF COMPUTERS, , 25, 430-439 (2008)

일반학술지

• 고속 System-in-Package 인터커넥트 기술 동향, IDEC Newsletter, , 192, 10-13 (2013)

• A Threshold Voltage Variation Calibration Algorithm for An ISFET-Based Low-Cost pH Sensor System, IEEE SENSORS, 0, 0, – (2015)
• An Approximate Condition to Avoid Reverse Leakage Current in ReRAM Crossbar Design, IEEE INTERNATIONAL SOC DESIGN CONFERENCE, 0, 0, – (2015)
• A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design, IEEE/ACM INTERNATIONAL COMPUTER-AIDED DESIGN CONFERENCE, 0, 0, – (2015)
• An FPGA-Based Embedded System for Portable and Cost-Efficient Bio-sensing: A Low-Cost Controller for Biomedical Diagnosis, IEEE INTERNATIONAL CIRCUITS AND SYSTEMS SYMPOSIUM, 0, 0, – (2015)
• An Input Pole Tuned Switching Equalization Scheme for High-Speed Serial Links, IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 0, 0, – (2015)
• A Voltage-Scalable 10-b Pipelined ADC with Current- Mode Amplifier, PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 0, 0, – (2014)
• A 0.4 V Driving Multi-Touch Capacitive Sensor with the Driving Signal Frequency set to (n+0.5) Times the Inverse of the LCD VCOM Noise Period, IEEE 2014 ISCAS, 0, 0, – (2014)
• An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, 426-427 (2014)
• A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface, INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, – (2014)
• A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, 50-51 (2014)
• Full-speed USB 2.0 device용 Link및 Application Layer 칩, 대한전자전기공학회 추계종합학술대회, 0, 0, – (2013)
• All-digital USB 2.0 device Full-speed PHY 칩, 대한전자공학회 하계학술대회, 0, 0, – (2013)
• RC-dominant 채널의 간단한 전달함수 모델을 이용한 RC-dominant 인터커넥트 길이와 손실의 Trade-off 분석, 대한전자공학회, 0, 0, – (2013)
• Micro-second 레벨의 지연시간을 가지는 Voltage Controlled Delay Line, 2012년도 대한전자공학회 하계학술대회 제 35권 1호, 0, 0, – (2012)
• An analytical model of scaled RC-dominant wires for high-speed wireline transceiver design, PROCEEDINGS OF INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 0, 0, – (2011)
• Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects, PROCEEDINGS OF HIGH PERFORMANCE INTERCONNECTS, 0, 0, – (2009)
• A Fractionally Spaced Linear Receive Equalizer with Voltage-to-Time Conversion, IEEE INTERNATINOAL SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS, 0, 0, – (2009)
• A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, – (2009)
• A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS Technology, IEEE INTERNAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 0, 0, – (2009)
• Equalized Interconnect for On-chip Network: Modeling and Optimization Framework, PROCEEDINGS OF IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, 0, 0, – (2007)
• Power-Adaptive Operational Amplifier with Positive Feedback Self-Biasing, PROCEEDINGS OF IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 0, 0, – (2006)

• 수신 단 TIA 터미네이션 기법의 단일 신호선 듀오바이너리 송수신 단 회로, ., 0, 0, – (2014)
• LCD VCOM Noise 주파수 (n+0.5) 배의 주파수를 인가 신호 주파수로 이용하는 다중 정전용량 터치 센서, ., 0, 0, – (2014)
• 오픈루프 시간차이 증폭기를 이용한 고해상도 Time-to-Digital Converter, ., 0, 0, – (2014)
• USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling, ., 0, 0, – (2014)
• CMOS 이미지 센서 인터페이스용 Gb/s SerDes, ., 0, 0, – (2014)
• An Experimental Verification of A Scaled RC-dominant Interconnect Line Model of High-speed Wireline, ., 0, 0, – (2014)
• A Single-Stage 40dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Analog Front End, ., 0, 0, – (2014)
• A Winner-Take-All Neuromorphic IC in 65nm CMOS, ., 0, 0, – (2014)
• Verilog Synthesis of USB 2.0 Full-speed Device PHY IP, ., 0, 0, – (2013)
• A Power Reduction of 37% in a Differential Serial Link Transceiver by Increasing the Termination Resistance, ., 0, 0, – (2013)
• High slew-rate 1.2V Class-AB OTA, ., 0, 0, – (2013)
• A Neuromorphic IC with Spike-Timing-Dependent-Plasticity, ., 0, 0, – (2013)
• A Winner-Take-All Neuromorphic IC in 65nm CMOS, ., 0, 0, – (2013)
• A Neuromorphic IC with Spike-Timing-Dependent-Plasticity, ., 0, 0, – (2013)
• A spread Spectrum Clock Generator Using Phase/Frequency Boosting with a Peak Power Reduction 14.6dB, RMS Jitter 1.45ps and Power 4.8mW/GHz for USB 3.0, ., 0, 0, – (2012)
• 실리콘 인터포저 인터커넥트 연구동향, ., 0, 0, – (2012)
• NCO용 Pulse Width Modulator 회로, ., 0, 0, – (2012)
• Future State-of-the-Art Electrical Interconnect, ., 0, 0, – (2010)
• Energy Efficient Wireline Communication Over RC-dominant Channels, ., 0, 0, – (2009)

• 생체-화학-전기 검출기 개발을 위한 다 학제간 교류 및 공동 연구 기획, 포항공과대학교 (2012-2013)
• NANO소자의 불확실성에 영향을 적게 받는 인터커넥트 연구, 포항공과대학교 (2012-2013)
• 실리콘 인터포저와 칩 적층 기법을 이용한 3D IC SIP용 차세대 저전력 초고속 인터커넥트 회로 및 융합설계에 관한 포괄적 연구, 재단법인한국연구재단 (2012-2013)
• 학부생연구프로그램-김도윤(전자)-계수에러에 강력한 트랜스미트 피드 포워드 이궐라이제이션 분석, 포항공과대학교 (2012-2012)
• POSTECH-삼성전자 RERAM 클러스터 연구과제(김병섭), 삼성전자(주) (2012-2013)
• NANO소자의 불확실성에 영향을 적게 받는 인터커넥트 연구, 포항공과대학교 (2013-2014)
• 신규부임교수 기자재지원비(학과부담), 포항공과대학교 (2013-2014)
• 학생인건비통합관리과제, 포항공대산학협력단 (2013-2020)
• 4.8350_1차년도 이월과제, 재단법인한국연구재단 (2013-2014)
• 실리콘 인터포저와 칩 적층 기법을 이용한 3D IC SIP용 차세대 저전력 초고속 인터커넥트 회로 및 융합설계에 관한 포괄적 연구, 재단법인한국연구재단 (2013-2014)
• 비침습형 유연바이오 센서구동 방법 개발/ 검증 및 시스템 초소형화 기술개발, 한국과학기술연구원 (2013-2013)
• 콘택트렌즈형 지속/자가구동 헬스 모니터링 플랫폼 기술 개발, 한국과학기술연구원 (2014-2014)
• NANO소자의 불확실성에 영향을 적게 받는 인터커넥트 연구(대학부담), 포항공대산학협력단 (2014-2015)
• 신규부임교수 기자재지원비(대학부담), 포항공대산학협력단 (2014-2015)
• 신규부임교수 기자재지원비(학과부담), 포항공과대학교 (2014-2015)
• 자체연구개발과제, 포항공과대학교 (2014-2025)
• 인건비풀링과제, 포항공대산학협력단 (2014-2015)
• POSTECH-삼성전자 RERAM 클러스터 연구과제(2차년도), 삼성전자(주) (2013-2014)
• 실리콘 인터포저와 칩 적층 기법을 이용한 3D IC SIP용 차세대 저전, 재단법인한국연구재단 (2014-2015)
• 4.9711/9752_2차년도 이월과제, 재단법인한국연구재단 (2014-2015)
• 포스텍-난양공대 실리콘 인터포저 인터커넥트 협력 연구 및 교류 프로그램, 재단법인한국연구재단 (2014-2015)
• POSTECH-삼성전자 RERAM 클러스터 연구과제(3차년도), 삼성전자(주) (2014-2015)
• 저전력 바이오센서 구동회로 개발, 한국과학기술연구원 (2015-2015)
• 실리콘 인터포저와 칩 적층 기법을 이용한 3D IC SIP용 차세대 저전력 초고속 인터커넥트 회로 및 융합설계에 관한 포괄적 연구, 재단법인한국연구재단 (2015-2016)
• 자체연구개발과제[2015년 신설], 포항공과대학교 (2015-2044)
• 저전력 바이오 센서 구동회로 개발, 한국과학기술연구원 (2015-2016)
• 코딩기법을 이용한 저항성 CROSS-POINT ARRAY 메모리의 성능 개선 연구, 에스케이하이닉스 주식회사 (2015-2016)
• 포스텍-난양공대 실리콘 인터포저 인터커넥트 협력 연구 및 교류 프로그램, 재단법인한국연구재단 (2015-2016)
• 4.11544 이월과제, 재단법인한국연구재단 (2015-2016)
• 실리콘 인터포저와 칩 적층 기법을 이용한 3D IC SIP용 차세대 저전력 초고속 인터커넥트 회로 및 융합설계에 관한 포괄적 연구, 재단법인한국연구재단 (2016-2017)

• 김병섭, 계수 오류에 강한 등화 송신기, 한국, 10-2015-0173193 (2015)
• 김병섭, 계수 오류 로버스트 피드포워드등화기, USA, 14/889,814 (2015)
• 김병섭, 계수 오류 로버스트 피드포워드등화기, USA, 14/889,814 (2015)
• 김병섭, 계수 오류 로버스트 피드포워드등화기, -, PCT/KR2014/0038 (2014)
• 김병섭, 계수 오류 로버스트 피드포워드등화기, 한국, 10-2014-0052097 (2014)
• 김병섭, 계수 오류 로버스트 피드포워드등화기, 한국, 10-2013-0051427 (2013)