국제 전문 학술지

Novel Adaptive Power Gating Strategy and Tapered TSV Structure in Multi-layer 3D IC, ACM Transactions on Design Automation of Electronic Systems 21(3), 44 (2016)

Wakeup Scheduling and Its Buffered Tree Synthesis for Power Gating Circuits, Integration, the VLSI journal 53, 157-170 (2016)

Synthesis of Dual-Mode Circuits through Library Design, Gate Sizing, and Clock Tree Optimization, ACM Transactions on Design Automation of Electronic Systems 21(3), 51 (2016)

An Improved Methodology for Resilient Design Implementation, ACM Transactions on Design Automation of Electronic Systems 20(4), 1-26 (2015)

Many-Core Token-Based Adaptive Power Gating, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(8), 1288–1292 (2013)

Enhancing the Efficiency of Energy-Constrained DVFS Designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21(10), 1769–1782 (2013), pp.

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(3), 404–417 (2012)

Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study, Proc. Design, Automation and Test in Europe (2018)

Optimal Static Gate Design for Synthesis of Ternary Logic Circuits, Proc. Asia and South Pacific Design Automation Conference (2018)

GRASP based Metaheuristics for Layout Pattern Classification, Proc. IEEE/ACM International Conference on Computer-Aided Design (2017)

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization, Proc. ACM/IEEE Design Automation Conference (2017)

A Novel Ternary Multiplier based on Ternary CMOS Compact Model, Proc. IEEE International Symposium on Multiple-Valued Logic (2017)

A Novel Approximate Synthesis Flow for the Energy-Efficient FIR filter, Proc. IEEE International Conference on Computer Design (2016)

Skew control methodology for useful-skew implementation, Proc. International SoC Design Conference (2016)

An Optimal Operating Point By Using Error Monitoring Circuits with An Error-Resilient Technique, Proc. IFIP/IEEE International Conference on Very Large Scale Integration (2015)

Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC, Proc. IEEE International Symposium on Quality Electronic Design (2015)

Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models, Proc. IEEE International SoC Design Conference (2014)

A New Methodology for Reduced Cost of Resilience, Proc. Great Lakes Symposium on VLSI (2014)

High-Performance Gate Sizing with a Signoff Timer, Proc. IEEE/ACM International Conference on Computer-Aided Design (2013)

Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits, Proc. IEEE International Conference on Computer Design (2013)

Smart Non-Default Routing for Clock Power Reduction, Proc. ACM/IEEE Design Automation Conference (2013)

Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing Tools, Proc. IEEE System-Level Interconnect Prediction (2013)

Active-Mode Leakage Reduction with Data-Retained Power Gating, Proc. IEEE/ACM Design, Automation and Test in Europe (2013)

Sensitivity-Guided Metaheuristics for Accurate Discrete Gate Sizing, Proc. IEEE/ACM International Conference on Computer-Aided Design (2012)

TAP – Token-Based Adaptive Power Gating, Proc. International Symposium on Low Power Electronics and Design (2012)

Accuracy-Configurable Adder for Approximate Arithmetic Designs, Proc. ACM/IEEE Design Automation Conference (2012)

Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions, Proc. ACM International Symposium on Physical Design (2012)

MAPG: Memory Access Power Gating, Proc. IEEE/ACM Design, Automation and Test in Europe (2012)

Recovery-Driven Design: A Power Minimization Methodology for Error-Tolerant Processor Modules, Proc. ACM/IEEE Design Automation Conference (2010)

Toward Effective Utilization of Timing Exceptions in Design Optimization, Proc. International Symposium on Quality Electronic Design (2010)

Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs, Proc. International Symposium on High-Performance Computer Architecture (2010)

Slack Redistribution for Graceful Degradation Under Voltage Overscaling, Proc. IEEE Asia and South Pacific Design Automation Conference (2010)

국산 CPU 코어를 적용한 컨트롤러 SOC 개발, 산업통상자원부 (2015-2017)

지능형반도체 전문인력양성사업, 산업통상자원부 (2016-2018)

Power Analysis for Low Power Package, 삼성전자 (2016-2017)

Display Driver 설계 및 구현, 삼성 디스플레이 (2016-2017)

그래핀 기반 삼진로직 아키텍쳐 연구, 재단법인 한국연구재단 (2016-2021)

근사연산을 이용한 저전력 딥러닝 하드웨어, 재단법인 한국연구재단 (2017-2020)

페타급 연결을 위한 터너리 신경망 표준셀, 삼성전자 (2017-2020)

멤커패시터 아키텍쳐 구현을 위한 다중 정전용량 소재 개발, 재단법인 한국연구재단 (2017-2022)

카메라 기반 인공지능 시스템 개발, 산업통상자원부 (2017-2019)

A. B. Kahng, S. Kang, Accuracy configurable adders and methods, U.S. 9229686 (2014)

B. Park, A. Kahng, S. Kang, J. Lee, Data-Retained Power-Gating Circuit and Devices Including the Same, U.S. 9166567 (2013)

강석형, Defect Judgment Apparatus for the Optimized defect Process of an Optical Storing Medium, 한국 102004-0102362 (2007)

강석형, Device and Method for Determining a Defective Area on an Optical Media, U.S. 7849379 (2006)

강석형, Device and Method for Determining a Defective Area on an Optical Media, Taiwan 2006-38413 (2006)

강석형, Device and Method for Determining a Defective Area on an Optical Media, Japan 2006-164503 (2006)

강석형, Device and Method for Determining a Defective Area on an Optical Media, France 2879011-A1 (2006)