▣ Title : Software Solutions to Hardware Problems in the Billion-Transistor Era
▣ Speaker : 이재욱 교수 (성균관대학교) / Prof. Jae W. Lee (SungKyunKwan University)
▣ Time : 4. 13(금) 오후 2:00~3:30 / pm14:00~15:30, April 13 (Fri)
▣ Place : LG동 강당 (101호) / Room #101, LG Research Bldg.
▣ Hosted by : 김병섭 교수 (T. 279-2382) / Prof. Byung Sub Kim (T. 279-2382)   
    BK21 미래정보기술사업단 / BK21 Educational Institute of Future Information Technology
▣ Absteact : 
The computer industry’s success for the past three decades has been primarily driven by Moore’s Law, which states a long-term technology trend of the transistor count on a chip doubling every two years. The exponential increase in transistor count implies an exponential reduction in transistor size, which makes modern processor design more challenging than ever. With operating voltage remaining relatively constant, high-performance single-core processors hit a physical limit on the amount of power a chip can dissipate, called the Power Wall. This has caused an end to exponential increases in clock frequencies and forced an industry-wide shift to multicores. However, multicores are only a half solution to the problem since the difficult task of extracting and exploiting parallelism should be handled by software. In this talk, I will first present recent progress in software-only speculative pipeline parallelization and run-time parallelism adaptation to achieve scalable and robust performance on multicores. If time permits, I will also briefly introduce software-only techniques to improve fault tolerance in modern microprocessors.