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집적회로 설계 자동화 (VLSI CAD)
시스템온칩 설계 (SoC design)
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Professor Profile
Seokhyung Kang
ProfessorBackground
Education
2008.09 ~ 2013.09
UNIV. OF CALIFORNIA AT SAN DIEGO (박사-Computer Engineering)
1999.03 ~ 2001.02
POSTECH (석사-전자전기공학)
1995.03 ~ 1999.02
POSTECH (학사-전자전기공학)
Experience
Career
2014.08 ~ 2018.03
UNIST 전기전자컴퓨터공학부
2013.08 ~ 2014.08
QUALCOMM TECHNOLOGIES, INC. ASIC DESIGN AUTOMATION
2013-2014
Qualcomm Technologies, Inc
2001.02 ~ 2008.07
삼성전자 SOC DELOPMENT TEAM
2001-2008
삼성전자 SYS.LSI
Focus
Research Areas
Publications
Journals
CTRLB BackEndOfLine Configuration Optimization using CrossDomain Transferable Reinforcement Learning, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, , 45, 2164-2178 (2026 )
ASPDAC 2026 Strengthening Asias Expanding Role in Design Automation Research, IEEE Design and Test, , 43, 55-57 (2026 )
An area and power efficient ternary serial adder using phase composite ZnO stack channel FETs, Nanoscale Advances, , 7, 3508-3513 (2025 )
Subunitcellsegmented ferroelectricity in brownmillerite oxides by phonon decoupling, Nature Materials, , 24, 1228-1235 (2025 )
Configurable antiambipolar photoresponses for optoelectronic multivalued logic gates, APPLIED PHYSICS LETTERS, , 125, - (2024 )
Mobile Transformer Accelerator Exploiting Various Line Sparsity and TileBased Dynamic Quantization, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, , 43, 1808-1821 (2024 )
MAOpt Reinforcement LearningBased Analog Circuit Optimization Using MultiActors, IEEE Transactions on Circuits and Systems I Regular Papers, , 71, 2045-2056 (2024 )
Junctionless NegativeDifferentialResistance Device Using 2D VanDerWaals Layered Materials for Ternary Parallel Computing, Advanced Materials, , 36, - (2024 )
Optimizing Ternary Multiplier Design With Fast Ternary Adder, IEEE Transactions on Circuits and Systems II Express Briefs, , 70, 766-770 (2023 )
Lightweight Speaker Recognition in Poincare Spaces, IEEE SIGNAL PROCESSING LETTERS, , 29, 224-228 (2022 )
CHAMP Channel Merging Process for CostEfficient HighlyPruned CNN Acceleration, IEEE Transactions on Circuits and Systems I Regular Papers, , 69, 3308-3319 (2022 )
Construction of Realistic Placeandroute Benchmarks for Machine Learning Applications, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, , 42, 2030-2042 (2022 )
Demonstration of Antiambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits, ACS Nano, , 16, 10994-11003 (2022 )
A 40nm CryoCMOS Quantum Controller IC for Superconducting Qubit, IEEE Journal of SolidState Circuits, , 57, 3274-3287 (2022 )
Enhanced Power Delivery Pathfinding for Emerging 3D Integration Technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, , 29, 591-604 (2021 )
VariationAware SRAM Cell Optimization Using Deep Neural NetworkBased Sensitivity Analysis, IEEE Transactions on Circuits and Systems I Regular Papers, , 68, 1567-1577 (2021 )
LowPower Ternary Multiplication Using Approximate Computing, IEEE Transactions on Circuits and Systems II Express Briefs, , 68, 2947-2951 (2021 )
Reinforcement LearningBased Power Management Policy for Mobile Device Systems, IEEE Transactions on Circuits and Systems I Regular Papers, , 68, 4156-4169 (2021 )
FluctuationBased Fade Detection for Local Scene Changes, IEEE Access, , 9, 149732-149743 (2021 )
Selfselective ferroelectric memory realized with semimetalic graphene channel, NPJ 2D MATERIALS AND APPLICATIONS, , 5, - (2021 )
Compact Topologyaware Bus Routing for Design Regularity, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, , 39, 1744-1749 (2020 )
Proactive Scenario CharacteristicAware Online Power Management on Mobile Systems, IEEE ACCESS, , 8, 69695-69711 (2020 )
A Logic Synthesis Methodology for LowPower Ternary Logic Circuits, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS IREGULAR PAPERS, , 67, 3138-3151 (2020 )
FPGA controller design for highfrequency LLC resonant converters, IEEJ Journal of Industry Applications, , 9, 523-529 (2020 )
Additive Statistical Leakage Analysis Using Exponential Mixture Model, IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, , 39, 4985-4998 (2020 )
Enhanced Power Delivery Pathfinding for Emerging 3D Integration Technology, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS, , 29, 591-604 (2020 )
SmartGrid Video Retargeting With Spatiotemporal Grid Optimization, IEEE ACCESS, , 7, 127564-127579 (2019 )
Power Integrity Coanalysis Methodology for MultiDomain HighSpeed Memory Systems, IEEE Access, , , - (2019 )
Statistical Leakage Analysis Using Gaussian Mixture Model, IEEE Access, , 6, 51939-51950 (2018 )
SoftCorner Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems, IEEE Access, , 6, 60115-60127 (2018 )
Ternary Full Adder Using MultiThreshold Voltage Graphene Barristors, IEEE Electron Device Letters, , 39, 1948-1951 (2018 )
Novel Adaptive PowerGating Strategy and Tapered TSV Structure in Multilayer 3D IC, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, , 21, - (2016 )
Wakeup scheduling and its buffered tree synthesis for power gating circuits, INTEGRATIONTHE VLSI JOURNAL, , 53, 157-170 (2016 )
Synthesis of DualMode Circuits Through Library Design Gate Sizing and ClockTree Optimization, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, , 21, - (2016 )
International Journals
국제 전문 학술지
Novel Adaptive Power Gating Strategy and Tapered TSV Structure in Multi-layer 3D IC, ACM Transactions on Design Automation of Electronic Systems 21(3), 44 (2016)
Synthesis of Dual-Mode Circuits through Library Design, Gate Sizing, and Clock Tree Optimization, ACM Transactions on Design Automation of Electronic Systems 21(3), 51 (2016)
An Improved Methodology for Resilient Design Implementation, ACM Transactions on Design Automation of Electronic Systems 20(4), 1-26 (2015)
Many-Core Token-Based Adaptive Power Gating, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(8), 1288–1292 (2013)
Enhancing the Efficiency of Energy-Constrained DVFS Designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21(10), 1769–1782 (2013), pp.
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(3), 404–417 (2012)
Conference
Conference Papers
Efficient Downsampling in Hybrid Neural Networks using Adversarial Autoencoders, Proceedings Design Automation and Test in Europe DATE, , 0, - (2026)
TANGRAM A Novel ILPbased OnTrack Bus Routing via Placement and Compression of Polygons, Proceedings Design Automation and Test in Europe DATE, , 0, - (2026)
A Heterogeneous Graphbased Gate Sizer Integrating Graph Attention Network and Transformer, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 1442-1448 (2026)
REvolution An Evolutionary Framework for RTL Generation driven by Large Language Models, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 282-288 (2026)
AuMEDAL Adaptable Grid Router with Metal Edge Detection And Layer Integration, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 1294-1300 (2026)
RLFill TimingAware Fill Insertion using Reinforcement Learning, IEEEACM International Conference on ComputerAided Design Digest of Technical Papers ICCAD, , 0, - (2025)
FedEDA Federated Learning Framework for PrivacyPreserving Machine Learning in EDA, Proceedings Design Automation Conference, , 0, - (2025)
Late Breaking Results A Geometric Diffusion Model for Macro Placement Generation, Proceedings Design Automation Conference, , 0, - (2025)
Late Breaking Results FineTuning LLMs for Test Stimuli Generation, Proceedings Design Automation Conference, , 0, - (2025)
Improving LLMBased Verilog Code Generation with Data Augmentation and RL, Proceedings Design Automation and Test in Europe DATE, , 0, - (2025)
Neural Circuit Parameter Prediction for Efficient Quantum Data Loading, Proceedings Design Automation and Test in Europe DATE, , 0, - (2025)
Invited Artificial Netlist Generation for Enhanced Circuit Data Augmentation, PROCEEDINGS OF THE 2025 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN ISPD 2025, , 0, 163-163 (2025)
LIBMixer An allMLP Architecture for Cell Library Characterization towards Design Space Optimization, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 814-820 (2025)
PCOpt Partition and Conquestbased Optimizer using MultiAgents for Complex Analog Circuits, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 842-848 (2025)
ParaFormer A Hybrid Graph Neural Network and Transformer Approach for PreRouting Parasitic RC Prediction, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 513-519 (2025)
Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 676-682 (2025)
Improving Timing amp Power Tradeoff in Postplace Optimization Using Multiagent Reinforcement Learning, IEEEACM International Conference on ComputerAided Design Digest of Technical Papers ICCAD, , 0, - (2024)
Invited Acceleration on Physical Design Machine Learningbased Routability Optimization, 2023 ACMIEEE SYSTEM LEVEL INTERCONNECT PATHFINDING WORKSHOP SLIP 2023, , 0, - (2023)
Placement Initialization via Community Detection, 2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE ISOCC, , 0, 125-126 (2023)
Advanced Parasitic Capacitance Extraction using Active Learning, 2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE ISOCC, , 0, 349-350 (2023)
Soft ActorCritic Reinforcement LearningBased Optimization for Analog Circuit Sizing, 2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE ISOCC, , 0, 47-48 (2023)
Adaptive FSP Adaptive Architecture Search with Filter Shape Pruning, Proceedings of the Asian Conference on Computer Vision (ACCV), , 0, - (2022)
MCQA Multiconstraint qubit allocation for nearFTQC device, IEEEACM International Conference on ComputerAided Design Digest of Technical Papers ICCAD, , 0, - (2022)
CPR Crossbargrain Pruning for an RRAMbased Accelerator with Coordinatebased Weight Mapping, Proceedings IEEE International Conference on Computer Design VLSI in Computers and Processors, , 0, 336-343 (2022)
A fast and scalable qubitmapping method for noisy intermediatescale quantum computers, Proceedings Design Automation Conference, , 0, 13-18 (2022)
GANDummy Fill Timingaware Dummy Fill Method using GAN, Proceedings of the ACM Great Lakes Symposium on VLSI GLSVLSI, , 0, 177-181 (2022)
A CryoCMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits, Digest of Technical Papers IEEE International SolidState Circuits Conference, , 0, 362-364 (2022)
SignalIntegrityAware Interposer Bus Routing in 25D Heterogeneous Integration, Proceedings of Asia and South Pacific Design Automation Conference, , 0, 178-183 (2022)
A 55mWChannel 2to7 GHz Frequency Synthesizable QubitControlling Cryogenic Pulse Modulator for Scalable Quantum Computers, Digest of Technical Papers Symposium on VLSI Technology, , 0, - (2021)
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator, Proceedings Design Automation and Test in Europe DATE, , 0, 1809-1814 (2021)
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction, Proceedings of The International Symposium on MultipleValued Logic, , 0, 155-158 (2020)
MTCMOSbased Ternary to Binary Converter, Proceedings International SoC Design Conference ISOCC 2020, , 0, 5-6 (2020)
LowPower 4Trit CurrentSteering DAC for Ternary Data Conversion, Proceedings International SoC Design Conference ISOCC 2020, , 0, 254-255 (2020)
GRLC Gridbased runlength compression for energyefficient CNN accelerator, ACM International Conference Proceeding Series, , 0, - (2020)
Late breaking results Reinforcement learningbased power management policy for mobile device systems, Proceedings Design Automation Conference, , 0, - (2020)
Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling, Proceedings of the 2020 Design Automation and Test in Europe Conference and Exhibition DATE 2020, , 0, 1091-1096 (2020)
OutlierAware Timemultiplexing MAC for Higher EnergyEfficiency on CNNs, Proceedings 2019 International SoC Design Conference ISOCC 2019, , 0, 119-120 (2019)
Ternary Logic Synthesis with Modified QuineMcCluskey Algorithm, Proceedings of The International Symposium on MultipleValued Logic, , 0, 158-163 (2019)
Design of QuadEdgeTriggered Sequential Logic Circuits for Ternary Logic, Proceedings of International Symposium on MultipleValued Logic, , 0, 37-42 (2019)
Design of QuadEdgeTriggered Sequential Logic Circuits for Ternary Logic, Proceedings of The International Symposium on MultipleValued Logic, , 0, 37-42 (2019)
FenceRegionAware MixedHeight Standard Cell Legalization, Proceedings of the 2019 on Great Lakes Symposium on VLSI, , 0, - (2019)
Fenceregionaware mixedheight standard cell legalization, Proceedings of the ACM Great Lakes Symposium on VLSI GLSVLSI, , 0, 259-262 (2019)
Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study, Proc. Design, Automation and Test in Europe (2018)
Optimal Static Gate Design for Synthesis of Ternary Logic Circuits, Proc. Asia and South Pacific Design Automation Conference (2018)
Skew control methodology for useful-skew implementation, Proc. International SoC Design Conference (2016)
An Optimal Operating Point By Using Error Monitoring Circuits with An Error-Resilient Technique, Proc. IFIP/IEEE International Conference on Very Large Scale Integration (2015)
Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC, Proc. IEEE International Symposium on Quality Electronic Design (2015)
Analysis and Reduction of Voltage Noise of Multi-layer 3D IC with PEEC-based PDN and Frequency-dependent TSV models, Proc. IEEE International SoC Design Conference (2014)
A New Methodology for Reduced Cost of Resilience, Proc. Great Lakes Symposium on VLSI (2014)
High-Performance Gate Sizing with a Signoff Timer, Proc. IEEE/ACM International Conference on Computer-Aided Design (2013)
Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits, Proc. IEEE International Conference on Computer Design (2013)
Smart Non-Default Routing for Clock Power Reduction, Proc. ACM/IEEE Design Automation Conference (2013)
Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing Tools, Proc. IEEE System-Level Interconnect Prediction (2013)
Active-Mode Leakage Reduction with Data-Retained Power Gating, Proc. IEEE/ACM Design, Automation and Test in Europe (2013)
Sensitivity-Guided Metaheuristics for Accurate Discrete Gate Sizing, Proc. IEEE/ACM International Conference on Computer-Aided Design (2012)
TAP – Token-Based Adaptive Power Gating, Proc. International Symposium on Low Power Electronics and Design (2012)
Accuracy-Configurable Adder for Approximate Arithmetic Designs, Proc. ACM/IEEE Design Automation Conference (2012)
Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions, Proc. ACM International Symposium on Physical Design (2012)
MAPG: Memory Access Power Gating, Proc. IEEE/ACM Design, Automation and Test in Europe (2012)
Recovery-Driven Design: A Power Minimization Methodology for Error-Tolerant Processor Modules, Proc. ACM/IEEE Design Automation Conference (2010)
Toward Effective Utilization of Timing Exceptions in Design Optimization, Proc. International Symposium on Quality Electronic Design (2010)
Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs, Proc. International Symposium on High-Performance Computer Architecture (2010)
Slack Redistribution for Graceful Degradation Under Voltage Overscaling, Proc. IEEE Asia and South Pacific Design Automation Conference (2010)
A Parallel Analytical Legalization Algorithm via Alternating Direction Method of Multipliers, 2025 IEEEACM International Conference On Computer Aided Design (ICCAD), , 0, 1-8 (2025)
SO3Cell Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology Placement and Routing, 2025 IEEEACM International Conference On Computer Aided Design (ICCAD), , 0, 1-9 (2025)
Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low PowerArea Overhead, 2025 IEEEACM International Conference On Computer Aided Design (ICCAD), , 0, 1-9 (2025)
DiffusionEnhanced Graph Transformer with Reinforcement Learning for Transferable Analog Circuit Optimizer, 2025 IEEEACM International Symposium on Low Power Electronics and Design (ISLPED), , 0, 1-6 (2025)
TA3D TimingAware 3D IC Partitioning and Placement by Optimizing the Critical Path, MLCAD 2024 Proceedings of the 2024 ACMIEEE International Symposium on Machine Learning for CAD, , 0, - (2024)
PPARelevant ClusteringDriven Placement for LargeScale VLSI Designs, Proceedings Design Automation Conference, , 0, - (2024)
SkyPlace A New Mixedsize Placement Framework using Modularitybased Clustering and SDP Relaxation, Proceedings Design Automation Conference, , 0, - (2024)
HiLight A Comprehensive Framework For High Performance And LightWeight Scalability In Surface Code Communication, Proceedings Design Automation Conference, , 0, - (2024)
RLPTQ RLbased Mixed Precision Quantization for Hybrid Vision Transformers, Proceedings Design Automation Conference, , 0, - (2024)
QNSA Quantum Neural Simulated Annealing for Combinatorial Optimization, 2024 25TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2024, , 0, - (2024)
Improvement of Mixed Track Height StandardCell Placement, Proceedings Design Automation and Test in Europe DATE, , 0, - (2024)
CTRLB BackEndOfLine Configuration Pathfinding Using CrossTechnology Transferable Reinforcement Learning, Proceedings Design Automation and Test in Europe DATE, , 0, - (2024)
TransNet KnowledgeTransferring Analog Circuit Optimizer with a NetlistBased Circuit Representation, Proceedings Design Automation and Test in Europe DATE, , 0, - (2024)
VITTOGO VISION TRANSFORMER ACCELERATOR WITH GROUPED TOKEN PRUNING, Proceedings Design Automation and Test in Europe DATE, , 0, - (2024)
Unveiling the BlackBox Leveraging Explainable AI for FPGA Design Space Optimization, Proceedings Design Automation and Test in Europe DATE, , 0, - (2024)
ClusterNet Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks, IEEEACM International Conference on ComputerAided Design Digest of Technical Papers ICCAD, , 0, - (2023)
Routability Prediction and Optimization Using Explainable AI, IEEEACM International Conference on ComputerAided Design Digest of Technical Papers ICCAD, , 0, - (2023)
Machine Learningbased Fast Circuit Simulation for Analog Circuit Array, 2023 ACMIEEE 5th Workshop on Machine Learning for CAD MLCAD 2023, , 0, - (2023)
MultiSource Transfer Learning for Design Technology CoOptimization, Proceedings of the International Symposium on Low Power Electronics and Design, , 0, - (2023)
Reinforcement Learningbased Analog Circuit Optimizer using gmIDfor Sizing, Proceedings Design Automation Conference, , 0, - (2023)
FPGABased Accelerator for RankEnhanced and HighlyPruned BlockCirculant Neural Networks, Proceedings of the 2023 Design Automation Test in Europe (DATE 2023), , 0, - (2023)
RLLegalizer Reinforcement Learningbased Cell Priority Optimization in MixedHeight Standard Cell Legalization, 2023 Design Automation amp Test in Europe Conference amp Exhibition (DATE), , 0, - (2023)
Mobile Accelerator Exploiting Sparsity of MultiHeads Lines and Blocks in Transformers in Computer Vision, Proceedings Design Automation and Test in Europe DATE, , 0, - (2023)
Routability Prediction using Deep Hierarchical Classification and Regression, Proceedings Design Automation and Test in Europe DATE, , 0, - (2023)
MAOpt Reinforcement Learningbased Analog Circuit Optimization using MultiActors, Proceedings Design Automation and Test in Europe DATE, , 0, - (2023)
Graph Partitioning Approach for Fast Quantum Circuit Simulation, Proceedings of the Asia and South Pacific Design Automation Conference ASPDAC, , 0, 690-695 (2023)
Design and Evaluation Frameworks for Advanced RISCbased Ternary Processor, Proceedings of the 2022 Design Automation and Test in Europe Conference and Exhibition DATE 2022, , 0, 1077-1082 (2022)
Gigasample Data Acquisition Method for Highspeed DDR5 SDRAM, Proceedings International SoC Design Conference 2021 ISOCC 2021, , 0, 109-110 (2021)
Components Analysis on Audio Signal Mixtures, Proceedings International SoC Design Conference 2021 ISOCC 2021, , 0, 363-364 (2021)
Comparative Analysis between Verilog and Chisel in RISCV Core Design and Verification, Proceedings International SoC Design Conference 2021 ISOCC 2021, , 0, 59-60 (2021)
Ternary Sense Amplifier Design for Ternary SRAM, Proceedings International SoC Design Conference 2021 ISOCC 2021, , 0, 151-152 (2021)
Memcapacitor based Minimum and Maximum Gate Design, Proceedings International SoC Design Conference 2021 ISOCC 2021, , 0, 75-76 (2021)
Data Protection Method for Flash Memory in Serial Peripheral Interface, Proceedings International SoC Design Conference 2021 ISOCC 2021, , 0, 117-118 (2021)
Design and analysis of a lowpower ternary SRAM, Proceedings IEEE International Symposium on Circuits and Systems, , 0, - (2021)
MDARTS Multiobjective Differentiable Neural Architecture Search, Proceedings Design Automation and Test in Europe DATE, , 0, 1344-1349 (2021)
Approach to Improve the Performance Using Bitlevel Sparsity in Neural Networks, Proceedings Design Automation and Test in Europe DATE, , 0, 1516-1521 (2021)
Power Delivery Pathfinding for Emerging DietoWafer Integration Technology, Proc Design Automation and Test in Europe (DATE), , 0, 842-847 (2019)
Fast ChipPackagePCB Coanalysis Methodology for Power Integrity of Multidomain HighSpeed Memory A Case Study, Proc IEEEACM Design Automation and Test in Europe Conference Exhibition (DATE), , 0, - (2018)
An optimal gate design for the synthesis of ternary logic circuits, Proc Asia and South Pacific Design Automation Conference, , 0, - (2018)
GRASP based Metaheuristics for Layout Pattern Classification, Proc IEEEACM International Conference on ComputerAided Design, , 0, - (2017)
A preliminary analysis of domain coupling in package power distribution network, 2017 IEEE International Symposium on RadioFrequency Integration Technology RFIT 2017, , 0, 19-21 (2017)
Fast Predictive Useful Skew Methodology for TimingDriven Placement Optimization, Proc ACMIEEE Design Automation Conference, , 0, - (2017)
A Novel Ternary Multiplier based on Ternary CMOS Compact Model, Proc IEEE International Symposium on MultipleValued Logic, , 0, - (2017)
A Novel Design Methodology for Errorresilient Circuits in Nearthreshold Computing, International Conference on Consumer Electronics (ICCE) Asia, , 0, - (2016)
Skew control methodology for usefulskew implementation, International SoC Design Conference (ISOCC), , 0, - (2016)
A Novel Approximate Synthesis Flow for the EnergyEfficient FIR filter, Proc IEEE International Conference on Computer Design, , 0, - (2016)
Highlights
Research Achievements
멤커패시터 아키텍쳐 구현을 위한 다중 정전용량 소재 Development, 재단법인 Korea연구재단 (2017-2022)
그래핀 기반 삼진로직 아키텍쳐 연구, 재단법인 Korea연구재단 (2016-2021)
근사연산을 이용한 Low-Power 딥러닝 하드웨어, 재단법인 Korea연구재단 (2017-2020)
페타급 연결을 위한 터너리 신경망 표준셀, Samsung Electronics (2017-2020)
카메라 기반 인공지능 시스템 Development, 산업통상자원부 (2017-2019)
지능형반도체 전문인력양성사업, 산업통상자원부 (2016-2018)
국산 CPU 코어를 적용한 컨트롤러 SOC 개발, 산업통상자원부 (2015-2017)
Power Analysis for Low Power Package, 삼성전자 (2016-2017)
Display Driver 설계 및 구현, 삼성 디스플레이 (2016-2017)
학생인건비통합관리과제, 포항공대산학협력단 (2018-2040)
자체연구Development과제[2015년 신설], POSTECH (2020-2040)
S_직접비_강석형, 포항공과대학교 (2021-2025)
S_간접비_강석형, 포항공과대학교 (2021-2025)
머신 러닝 기반 설계 자동화/최적화 소프트웨어 Development, Samsung Electronics(주) (2022-2025)
인공지능 반도체 설계 SW(SOFTWARE) 개발, 정보통신기획평가원 (2024-2025)
생성형 AI 모델을 활용한 ARTIFICIAL DESIGN 생성, 삼성전자(주) (2024-2025)
SKYPLACE: OPEN-SOURCE VLSI PLACEMENT FRAMEWORK, Google Asia Pacific (2024-2025)
AI 프로세서의 데이터 특성과 데이터 접근 특성에 최적화한 비휘발성 PIM용 메모리 모듈 및 메모리 컴파일러 개발, 정보통신기획평가원 (2025-2025)
DRAM PIM 설계 기반 기술개발, 정보통신기획평가원 (2025-2025)
선단 노드에서의 회로 설계 최적화 및 편의를 위한 DUMMY FILL 방법론 개선, 삼성전자(주) (2023-2024)
디스플레이 패널 성능 예측을 위한 AI 모델 개발 (3차), 엘지디스플레이(주) (2023-2024)
A HYPERPARAMETER-FREE VLSI GLOBAL PLACEMENT , Google Asia Pacific (2023-2024)
AI 프로세서의 데이터 특성과 데이터 접근 특성에 최적화한 비휘발성 PIM용 메모리 모듈 및 메모리 컴파일러 개발, 정보통신기획평가원 (2024-2024)
DRAM PIM 설계 기반 기술개발, 정보통신기획평가원 (2024-2024)
4.0026616_이월과제, 정보통신기획평가원 (2024-2024)
4.0025286/4.0026016_이월과제, 정보통신기획평가원 (2024-2024)
인공지능 기반 반도체 설계 최적화, 재단법인Korea연구재단 (2024-2024)
디락 반금속 기반 초고속 저전력 X-POINT 비휘발성 메모리, 울산과학기술원 (2019-2023)
GIGA-SAMPLING기반 DATA ACQUISITION 기법 연구, 에스케이하이닉스 주식회사 (2022-2023)
INTEL QUARTUS-AUTOTUNER, PRECISION INNOVATIONS INC (2022-2023)
디스플레이 패널 성능 예측을 위한 AI 모델 개발, 엘지디스플레이(주) (2022-2023)
4.0024341_이월과제, 정보통신기획평가원 (2023-2023)
DRAM PIM 설계 기반 기술개발, 정보통신기획평가원 (2023-2023)
인공지능 반도체 설계 SW(SOFTWARE) 개발, 정보통신기획평가원 (2023-2023)
4.0023292/4.0024032_이월과제, 정보통신기획평가원 (2023-2023)
AI 프로세서의 데이터 특성과 데이터 접근 특성에 최적화한 비휘발성 PIM용 메모리 모듈 및 메모리 컴파일러 개발, 정보통신기획평가원 (2023-2023)
FPGA 기반 저전력 비전 트랜스포머 가속기 구현, 재단법인한국연구재단 (2023-2023)
3진법/4진법을 이해할 수 있는 이종접합 구조체 기반 반도체 소자 및 회로 Development, 성균관대학교산학협력단 (2020-2022)
양산향 BLOCK STD CELL USAGE를 고려한 VIRTUAL NETLIST 개발, 삼성전자(주) (2021-2022)
FPGA 기반 무인 잠수정 실시간 자동 영상표적인식 모델 개발, 엘아이지넥스원(주) (2021-2022)
디스플레이 패널 성능 예측을 위한 AI 모델 개발, 엘지디스플레이(주) (2021-2022)
인공지능 반도체 설계 SW(SOFTWARE) 개발, 정보통신기획평가원 (2022-2022)
4.0022210_이월과제, 정보통신기획평가원 (2022-2022)
포스코-포스텍 연계창업 관련 딥러닝 기반의 반도체 설계 자동화 연구, 포스코홀딩스(주) (2022-2022)
DRAM PIM 설계 기반 기술개발, 정보통신기획평가원 (2022-2022)
딥러닝 기반 설계 자동화 기술 자문, 주식회사 애자일소다 (2022-2022)
포스코-포스텍 연계창업 관련 딥러닝 기반의 반도체 설계 자동화 연구 (2차), 포스코홀딩스(주) (2022-2022)
강석형_신규부임교수 연구비지원(3차_학과), POSTECH (2020-2021)
강석형_신규부임교수 연구비지원(3차_대학), POSTECH (2020-2021)
강석형_신규임교수 기자재지원 (3차_대학), POSTECH (2020-2021)
강석형_신교수 기자재지원(3차_학과), POSTECH (2020-2021)
GIGA-SAMPLING기반 DATA ACQUISITION 기법 연구, 에스케이하이닉스 주식회사 (2021-2021)
ABOV A31R210 QSPI/QEI 개발 자문, 어보브반도체 주식회사 (2021-2021)
인공지능 반도체 설계 SW(SOFTWARE) 개발, 정보통신기획평가원 (2021-2021)
4.16504 이월과제, 재단법인Korea연구재단 (2019-2020)
강석형_신규부임교수 기자재지원(2차_대학), POSTECH (2019-2020)
강석형_신규부임교수 기자재지원(2차_학과), POSTECH (2019-2020)
강석형_신규부임교수 연구비지원(2차_학과), POSTECH (2019-2020)
강석형_신규부임교수 연구비지원(2차_대학), POSTECH (2019-2020)
근사연산을 이용한 Low-Power 딥러닝 하드웨어 설계, 재단법인Korea연구재단 (2019-2020)
실시간 센서 정보 처리가 가능한 자율주행 기반 물류로봇 Development, 중소기업기술정보진흥원 (2019-2020)
4.16915_이월과제, 중소기업기술정보진흥원 (2019-2020)
근사연산을 이용한 Low-Power 딥러닝 하드웨어 설계, 재단법인Korea연구재단 (2020-2020)
4.17727/18503 이월과제, 재단법인Korea연구재단 (2020-2020)
강석형_신규부임교수 기자재지원(1차_대학), POSTECH (2018-2019)
강석형_신규부임교수 연구비지원(1차_학과_), POSTECH (2018-2019)
강석형_신규부임교수 연구비지원(1차_대학), POSTECH (2018-2019)
강석형_신규부임교수 기자재지원(1차_학과), POSTECH (2018-2019)
근사연산을 이용한 Low-Power 딥러닝 하드웨어 설계, 재단법인Korea연구재단 (2018-2019)
주행환경 탐지 및 도로객체 인식의 동시, 실시간 처리가 가능한 카메라 기반 인공지능 시스템 Development(2차), Korea산업기술기획평가원 (2018-2019)
머신 러닝 기반 VLSI 설계 자동화, 삼성전자(주) (2019-2019)
주행환경 탐지 및 도로객체 인식의 동시, 실시간 처리가 가능한 카메라 기반 인공지능 시스템 Development, Korea산업기술기획평가원 (2017-2018)
Intellectual Property
IP
강석형,김준형,송원호,박진영,정성철,박기복,조재형, 비휘발성 메모리 장치 및 그의 동작 방법, 한국, 10-2025-0051476 (P202)
강석형,민경준,박성현,조진오,박현우, 데이터 증강 및 강화학습을 활용하여 베릴로그 코드 생성을 위한 거대 언어 모델을 트레이닝하는 방법 및 장치, 한국, 10-2025-0145410 (IP25)
강석형,조진오,박성현,이자강,이승윤,안진모, 모방학습 및 강화학습 기반의 타이밍을 고려하여 집적 회로를 설계하는 방법 및 장치, 한국, 10-2025-0145475 (IP25)
강석형,서재민,박세진, 다중 에이전트 강화학습을 활용하여 디지털회로 타이밍 및 전력을 동시에 결정하는 방법 및 장치, 한국, 10-2025-0106678 (IP25)
강석형,이재승,장성규,이자강, 인공지능을 이용하여 표준 통합 셀 라이브러리를 특성화하는 방법 및 장치, 한국, 10-2025-0108502 (IP25)
강석형,이자강,김형옥,박성현,이재승, DTCO(DESIGN TECHNOLOGY CO-OPTIMIZATION)를 수행하는 집적 회로 설계 시스템, 한국, 10-2024-0065267 (IP24)
강석형,최영창,이경수,최민정, 전기적 디자인 변수를 이용한 강화학습 기반의 아날로그 회 로 최적화 방법 및 이를 수행하는 시스템, 한국, 10-2024-0070997 (IP24)
강석형,윤종호,송해나,오태현,김도훈,권은지, 컴퓨팅 시스템, 신경망 훈련 및 압축 방법, 및 신경망 연산 가속기, 한국, 10-2024-0036087 (IP23)
강석형,권은지, 가지치기 및 양자화를 이용한 트랜스포머 가속 방법 및 그 장치, 한국, 10-2024-0051528 (IP23)
강석형,김도훈,심재윤,박성혜, 다중 제약 조건 큐비트 할당 방법 및 이를 이용하는 양자 장치, USA, 18/542,385 (2023)
강석형,임재경, 양자 회로 시뮬레이션 장치 및 방법, Korea, 10-2023-0182284 (2023)
강석형,이자강,김대연, 계층적 분류 및 회귀 모델을 이용하는 라우팅 가능성 예측 방법 및 장치, 계층적 분류 및 회귀 모델을 학습하는 전이 학습 방법, Korea, 10-2024-0032668 (2023)
강석형,박성혜,권민혁,심재윤, 큐비트 매핑 방법 및 이를 사용하는 양자 컴퓨터, Korea, 10-2023-0156509 (2023)
강석형,박성혜,김도훈,심재윤, 다중 제약 조건 큐비트 할당 방법 및 이를 이용하는 양자 장치, Korea, 10-2023-0125128 (2023)
강석형,김선민,최영창,이경수, 저전력 삼진 정적랜덤접근메모리 셀, USA, 18/060,223 (2022)
강석형,박기복,정성철,박진영,조재형,김준형,송원호, 비휘발성 메모리 장치 및 그의 동작 방법, USA, 17/969,123 (2022)
강석형,김준형,송원호,박진영,정성철,박기복,조재형, 비휘발성 메모리 장치 및 그의 동작 방법, Korea, 10-2022-0102892 (2022)
강석형,박기복,정성철,박진영,조재형,김준형,송원호, 양극성 채널 트랜스컨덕턴스 스위칭 기반 비휘발성 교차점 메모리, Korea, 10-2021-0143329 (2022)
강석형,최영창,김선민,이경수, 다른 문턱 전압들을 갖는 트랜지스터들을 포함하는 인버터 및 이를 포함하는 메모리 셀, Korea, 10-2022-0134349 (2022)
강석형,이승규,권은지,강예성, 하드웨어 가속기 성능을 개선시키기 위한 합성곱 신경망의 연산 순서 조정을 위한 장치 및 방법, Korea, 10-2021-0156873 (2021)
강석형,최영창,김선민,백승한, 삼진-이진 변환기 및 이의 삼진-이진 변환 방법, 및 이진-삼진 변환기 및 이의 이진-삼진 변환 방법, Korea, 10-2021-0131931 (2021)
강석형,최영창,김선민,백승한, 삼진 곱셈기, Korea, 10-2021-0131932 (2021)
강석형,김대연, 인공 합성 회로 생성 방법 및 인공 합성 회로 생성 장치, Korea, 10-2021-0174748 (2021)
강석형,최영창,김선민,이경수, Low-Power 삼진 정적랜덤접근메모리 셀, Korea, 10-2021-0168696 (2021)
강석형,백승한,김선민,최영창, 삼진-이진 변환기, Korea, 10-2021-0098897 (2021)
강석형,김선민,백승한,최영창, 삼진 곱셈기, Korea, 10-2021-0098899 (2021)
강석형,박성혜,이승윤,김선민, 삼진 논리 회로 장치, USA, 17/489,624 (2021)
강석형,박성혜,이승윤,김선민, 삼진 논리 회로 장치, USA, 17/489,629 (2021)
강석형,박성혜,이승윤,김선민, 삼진 논리 회로 장치, Korea, 10-2021-0055864 (2021)
강석형,박윤호,강예성,권은지,김성훈, 특징 맵을 컴프레싱하는 장치 및 방법, Korea, 10-2021-0056723 (2021)
강석형,이승윤,김선민,박성혜, 저전력 삼진 논리 회로 장치, USA, 17/175,570 (2020)
강석형,박성혜,이승윤,김선민, 삼진 논리 회로 장치, Korea, 10-2021-0055863 (2020)
강석형,이승윤,김선민,박성혜, Low-Power 삼진 논리 회로 장치, Korea, 10-2020-0129024 (2020)
강석형,김성훈,박윤호,강예성, 신경망 가속기 및 그것의 동작 방법, USA, 16/751,503 (2020)
강석형,이승윤,김선민, 변조 퀸맥클러스키 알고리즘을 이용한 삼진 논리 합성 장치 및 방법, USA, 16/714,583 (2019)
강석형,강예성,박윤호,김성훈, 신경망 가속기 및 그것의 동작 방법, Korea, 10-2019-0034583 (2019)
강석형,박윤호,김성훈,강예성, 신경망 가속기 및 그것의 동작 방법, Korea, 10-2019-0034583 (2019)
강석형,김성훈,강예성,박윤호, 신경망 가속기, Korea, 10-2019-0010293 (2019)
강석형,이승윤,김선민, 변조 퀸맥클러스키 알고리즘을 이용한 삼진 논리 합성 장치 및 방법, Korea, 10-2018-0173933 (2018)
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B. Park, A. Kahng, S. Kang, J. Lee, Data-Retained Power-Gating Circuit and Devices Including the Same, U.S. 9166567 (2013)
강석형, Defect Judgment Apparatus for the Optimized defect Process of an Optical Storing Medium, 한국 102004-0102362 (2007)
강석형, Device and Method for Determining a Defective Area on an Optical Media, U.S. 7849379 (2006)
강석형, Device and Method for Determining a Defective Area on an Optical Media, Taiwan 2006-38413 (2006)
강석형, Device and Method for Determining a Defective Area on an Optical Media, Japan 2006-164503 (2006)
강석형, Device and Method for Determining a Defective Area on an Optical Media, France 2879011-A1 (2006)
강석형,민경준,박성현,조진오,박현우, 데이터 증강 및 강화학습을 활용하여 베릴로그 코드 생성을 위한 거대 언어 모델을 트레이닝하는 방법 및 장치, USA, 19/536,382 (P202)
강석형,서재민,박세진, 다중 에이전트 강화학습을 활용하여 디지털회로 타이밍 및 전력을 동시에 결정하는 방법 및 장치, USA, 19/410,408 (P202)
강석형,이재승,장성규,이자강, 인공지능을 이용하여 표준 통합 셀 라이브러리를 특성화하는 방법 및 장치, 대만, 114150026 (P202)
강석형,이재승,장성규,이자강, 인공지능을 이용하여 표준 통합 셀 라이브러리를 특성화하는 방법 및 장치, USA, 19/425,116 (P202)
강석형,이자강,김형옥,박성현,이재승, DTCO(DESIGN TECHNOLOGY CO-OPTIMIZATION)를 수행하는 집적 회로 설계 시스템, USA, 18/979,005 (P202)
강석형,최영창,이경수,최민정, 전기적 디자인 변수를 이용한 강화학습 기반의 아날로그 회로 최적화 방법 및 이를 수행하는 시스템, USA, 18/926,778 (P202)
강석형,윤종호,송해나,오태현,김도훈,권은지, 컴퓨팅 시스템, 신경망 훈련 및 압축 방법, 및 신경망 연산 가속기, USA, 18/925,872 (P202)
강석형,권은지, 가지치기 및 양자화를 이용한 트랜스포머 가속 방법 및 그 장치, USA, 19/057,788 (P202)
강석형,임재경, 양자 회로 시뮬레이션 장치 및 방법, USA, 18/969,097 (P202)
강석형,박성혜,권민혁,심재윤, 큐비트 매핑 방법 및 이를 사용하는 양자 컴퓨터, USA, 18/618,898 (P202)
강석형,박기복,정성철,박진영,조재형,김준형,송원호, 양극성 채널 트랜스컨덕턴스 스위칭 기반 비휘발성 교차점 메모리, USA, 19/716,414 (P202)
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