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Professor Profile

Seon-Kyoo Lee

JA Professor
Position

JA Professor

Lab

Integrated Circuits and Systems Lab · C5 Room 419-4

Visit Homepage Send Email sites.google.com/view/icsdlab

Background

Education

2
2006.03 ~ 2012.08

POSTECH (통합-전자전기공학)

2004.02 ~ 2006.02

한양대학교 (학사-전자전기컴퓨터공학)

Experience

Career

4
2019.03 ~ 2023.08

Samsung Electronics 메모리사업부

2012.09 ~ 2023.08

Samsung Electronics

2012.09 ~ 2019.02

Samsung Electronics 메모리사업부

2011.08 ~ 2012.07

UNIV. OF MICHIGAN

Focus

Research Areas

4
High-speed / Low-power Interface Circuits Design
On-chip Interconnect Circuits Design
Memory Interface Circuits Design
Analog & Mixed-mode Circuits Design

Publications

Journals

16

International Journals

A 20GbsLine SingleEnded Transceiver With CouplingBalanced CrosstalkCancellation for ShieldLess 15μmPitch Interconnect, IEEE Journal of SolidState Circuits, , 61, - (2026 )
A 94fs Jitter and −2493dB FoM MDLL With Background Calibration of Injection Phase and SlewRate Mismatch, IEEE Journal of SolidState Circuits, , , - (2026 )
A 20Gbs 4tap timedomain DFE with pulse width modulation for a DQDQS matched parallel receiver, Electronics Letters, , 60, - (2024 )
A 18GbsPin 16Tb NAND Flash Memory MultiChip Package With FChip for HighPerformance and HighCapacity Storage, IEEE Journal of SolidState Circuits, , 56, 1129-1140 (2021 )
A 05V 147mu W 40kSs 13bit SAR ADC With Capacitor Error Compensation, IEEE Transactions on Circuits and Systems II Express Briefs, , 61, 840-844 (2014 )
CurrentMode Transceiver for Silicon Interposer Channel, IEEE Journal of SolidState Circuits, , 49, 2044-2053 (2014 )
A 5 Gbs SingleEnded Parallel Receiver With Adaptive CrosstalkInduced Jitter Cancellation, IEEE Journal of SolidState Circuits, , 48, 2118-2127 (2013 )
A QDRBased 6GBs Parallel Transceiver With CurrentRegulated VoltageMode Output Driver and Byte CDR for Memory Interface, IEEE Transactions on Circuits and Systems II Express Briefs, , 60, 91-95 (2013 )
A Wide LockRange Referenceless CDR with Automatic Frequency Acquisition, Journal of Electrical and Computer Engineering, , , - (2011 )
A 21 fJConversionStep 100 kSs 10bit ADC With a LowNoise TimeDomain Comparator for LowPower Sensor Interface, IEEE Journal of SolidState Circuits, , 46, 651-659 (2011 )
A 110 MHz to 14 GHz Locking 40Phase AllDigital DLL, IEEE Journal of SolidState Circuits, , 46, 435-444 (2011 )
A 1GHz Digital PLL With a 3ps Resolution FloatingPointNumber TDC in a 018mu m CMOS, IEEE Transactions on Circuits and Systems II Express Briefs, , 58, 70-74 (2011 )
A 1 GHz ADPLL With a 125 ps MinimumResolution SubExponent TDC in 018 mu m CMOS , IEEE Journal of SolidState Circuits, , 45, 2874-2881 (2010 )
Inactivation of S mutans Using an Atmospheric Plasma Driven by a PalmSizeIntegrated Microwave Power Module, IEEE Transactions on Plasma Science, , 38, 1956-1962 (2010 )
FEXTeliminated stubalternated microstrip line for multigigabitsecond parallel links, Electronics Letters, , 44, 272-273 (2008 )

Domestic Journals

A SSNReduced 5Gbs Parallel Transmitter, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, , 7, 235-240 (2007 )

Conference

Conference Papers

20
A 128Gbs Parallel Receiver with a OneWay SelfTraining Scheme for Equalizing ISI and Reflections in MultiDrop Memory Interfaces, Digest of Technical Papers IEEE International SolidState Circuits Conference, , 0, 636-638 (2026)
A 087pJb 17Gbspin Parallel Receiver with a Local DQS Recovery for a SupplyNoiseTolerant DQS Distribution in HighPerformance NAND Flash Interfaces, Digest of Technical Papers IEEE International SolidState Circuits Conference, , 0, 638-640 (2026)
A 94fsrmsJitter and 2493dB FoM 40GHz RingOscillatorBased MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch, Digest of Technical Papers Symposium on VLSI Technology, , 0, - (2024)
A 246fJb 133Tbsmm SingleEnded CurrentMode Transceiver with Crosstalk Cancellation for ShieldLess ShortReach Interconnect, Digest of Technical Papers Symposium on VLSI Technology, , 0, - (2024)
Issues and key technologies for next generation 3D NAND, 2021 International Conference on Electronics Information and Communication ICEIC 2021, , 0, - (2021)
Issues and key technologies for next generation 3D NAND, 2021 International Conference on Electronics Information and Communication ICEIC 2021, 0, 0, - (2021)
A 18 Gbspin 16Tb NAND Flash Memory MultiChip Package with FChip of Toggle 40 Specification for High Performance and High Capacity Storage Systems, IEEE Symposium on VLSI Circuits Digest of Technical Papers, , 0, - (2020)
A 128Gb 2bcell NAND flash memory in 14nm technology with tPROG640µs and 800MBs IO rate, Digest of Technical Papers IEEE International SolidState Circuits Conference, , 0, 138-139 (2016)
1GBs 2Tb NAND flash multichip package with frequencyboosting interface chip, Digest of Technical Papers IEEE International SolidState Circuits Conference, , 0, 138-139 (2015)
A 95fJb CurrentMode Transceiver for 10mm OnChip Interconnect, ISSCC, , 0, 262-264 (2013)
A 05V 113μW 1kSs Resistive Sensor Interface Circuit with Correlated Double Sampling, CICC, , 0, - (2012)
A 5Gbs SingleEnded Parallel Receiver with Adaptive FEXT Cancellation, ISSCC, , 0, 140-141 (2012)
An 8GBs QuadSkewCancelling Parallel Transceiver in 90nm CMOS for HighSpeed DRAM Interface, ISSCC, , 0, 136-137 (2012)
HighSpeed Links for Memory Interface, ICICDT, , 0, 16-19 (2010)
A 1GHz ADPLL with a 125ps MinimumResolution SubExponent TDC in 018um CMOS, INTERNATIONAL SOLIDSTATE CIRCUITS CONFERENCE, , 0, - (2010)
A 13uW 06V 87ENOB Successive Approximation ADC in a 018um CMOS, SYMPOSIUM ON VSLI CIRCUITS, , 0, - (2009)
A 650Mbsto8Gbs Referenceless CDR Circuit with Automatic Acquisition of Data Rate, ISSCC, , 0, - (2009)
A 650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate, , 0, 0, - (2009)
A 8 GBytes Transceiver with CurrentBalanced PseudoDifferential Signaling for Memory Interface, ASSCC, , 0, - (2008)
A 5Gbs 16bit Transmitter with Segmented GroupInversion Encoding, ISOCC, , 0, - (2007)

Highlights

Research Achievements

3
고성능 NAND IO 회로 및 인공지능 기반 설계기법 연구, 삼성전자(주) (2024-2027)
이선규 신규부임교수 초기정착비(2차)/학과, POSTECH (2024-2025)
이선규 신규부임교수 초기정착비(1차/학과), POSTECH (2023-2024)

Intellectual Property

IP

14
이선규,김승범,이재호,심재윤, 크로스토크 제거를 위한 방법, 장치 및 시스템, 한국, 10-2026-0182592 (P202)
이선규,문지원,심재윤, 채널 반사파 특성 추출 회로 및 이를 포함하는 메모리 장치, 한국, 10-2026-0054101 (P202)
이선규,김병찬,심재윤,이경수, 수신기를 포함하는 전자 장치 및 전자 장치의 동작 방법, 한국, 10-2026-0062005 (P202)
이선규,김승범,이재호,심재윤, 고속 인터페이스를 위한 장치 및 방법, 한국, 10-2026-0099466 (IP25)
이선규,문지원,심재윤, 기준전압 스윕을 이용한 채널 특성 추출 회로 및 방법, 한국, 10-2026-0018246 (IP25)
이선규,김병찬,심재윤,이경수, 전원 노이즈 내성을 갖는 듀얼 DQS 트리 및 로컬 DQS 복구 회로를 포함하는 메모리 수신장치, 한국, 10-2026-0022781 (IP25)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, USA, 12/673,747 (2010)
심재윤,이선규, 시간 증폭기를 이용한 하위-지수 방식의 시간-디지털 변환기, USA, 12/795,221 (2010)
심재윤,이선규, 위상차 증대기를 이용한 하위-지수 방식의 시간-디지털 변환기, Korea, 10-2010-0044818 (2010)
심재윤,이선규, 아날로그 디지털 변환기의 시간영역 전압 비교기, USA, 12/663,732 (2010)
심재윤,이선규, 아날로그 디지털 변환기의 시간영역 전압 비교기, -, PCT/KR2009/0057 (2009)
심재윤,이선규, 아날로그 디지털 변환기의 시간영역 전압 비교기, Korea, 10-2009-0090204 (2009)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, -, PCT/KR2008/0012 (2007)
박홍준,이경호,심재윤,이선규, 수신단 누화잡음을 줄이는 수직 돌기 추가 마이크로 스트립 전송선, Korea, 10-2007-0085300 (2007)
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